The present invention relates to a semiconductor device and a method for testing a semiconductor device, and more particularly, to a semiconductor device and a method for testing a semiconductor device formed by connecting at least three independently accessible macro semiconductor memory devices connected to a semiconductor substrate.
A semiconductor device may be formed by connecting three or more independently accessible semiconductor memory devices, such as, dynamic random access memories (DRAMs), to a single semiconductor substrate. Each of the memory devices is referred to as a macro since it can be accessed independently. Evaluation tests are normally conducted on each of the macros.
FIG. 1 is a schematic block diagram showing a prior art semiconductor device 100.
The semiconductor device 100 has four independently accessible DRAMs 51, 52, 53, 54 connected to a semiconductor substrate 50. The first to fourth DRAMs 51-54 are each controlled, for example, by the same external device or independently with different external devices. Each of the DRAMs 51-54 is thus provided with an I/O terminal (not shown) connected to the associated external device.
The DRAMS 5-54 are also each controlled by a tester. The tester sends test signals to the DRAMs 51-54 through a common input terminal and signal line. As shown in FIG. 1, the test signals include a test mode signal TTST, a test clock enable signal TCKE, a test clock signal TCLK, a test chip select signal TXCS, a test row address strobe signal TXRAS, a test column address strobe signal TXCAS, a test write enable signal TXWE, test address signals TA0-TA9, and test write data TI.
Output data (test data) TQ0-TQ3 of the respective first to fourth DRAMs 51-54 must each be separately provided to the tester. Thus the first to fourth DRAMs 51-54 each have an output terminal and a signal line for each of the output data TQ0-TQ3.
When the tester tests the DRAMs 51-54, the various test signals are provided to the first to fourth DRAMs 51-54 through the common input terminal and signal line. The tester simultaneously commences testing of each of the DRAMs 51-54.
A memory capacity difference between the DRAMs 51-54 results in the shortcomings discussed below.
In one example, the first and second DRAMs 51, 52 each have a memory capacity of one megabit, the third DRAM 53 has a memory capacity of two megabits, and the fourth DRAM 54 has a memory capacity of four megabits. That is, the first and second DRAMs 51, 52 each have a DRAM core with an array block of one megabit, the third DRAM 53 has a DRAM core of two array blocks, and the fourth DRAM 54 has a DRAM core of four array blocks.
When the tester simultaneously commences testing of the DRAMs 51-54, the testing is completed first by the DRAMs having small memory capacities. That is, the testing of the one megabit first and second DRAMs 51, 52 are completed first, and the testing of the remaining two megabit third DRAM 53 and the four megabit fourth DRAM 54 is continued. Then, the testing of the third DRAM 53 is completed, and the testing of the fourth DRAM 54 is continued. Subsequently, the testing of the fourth DRAM 54 is completed.
Referring to FIG. 2, the semiconductor 100 is supplied with consumption current 11 during a first period t1 from when the testing is commenced to when the testing of the first and second DRAMs 51, 52 is completed. Then, the semiconductor 10 is supplied with consumption current I2 during a second period t2 from when the testing of the first and second DRAMs 51, 52 is completed to when the testing of the third DRAM 53 is completed. Afterward, the semiconductor 100 is supplied with consumption current I3 during a third period from when the testing of the third DRAM 53 is completed to when the testing of the fourth DRAM 54 is completed.
During the first test period t1 when the four DRAMs 51-54 are tested simultaneously, the power consumption of the semiconductor device 100 is maximum. The tester simultaneously tests a multiple number of the semiconductor devices. Thus, if the consumption current I1 is large, the tester must have a large current supplying capability. However, the current supplying capability can only be increased to a certain level. This limits the number of semiconductor devices that can be simultaneously tested. As a result, the testing cost and testing time are high.
It is an object of the present invention to provide a semiconductor device and a method for testing the semiconductor device that increases the number of semiconductor devices that can be simultaneously tested without increasing the current supplying capability of the tester.
To achieve the above object, the present invention provides a method for testing a semiconductor device including at least three memory devices. The memory devices are each independently accessible, and at least one memory device has a memory capacity differing from the other memory devices. The method includes the steps of serially testing at least two of the memory devices excluding the memory device having a test period that is longest among the memory devices, and testing the memory device having the longest test period in parallel with the memory devices being serially tested.
A further aspect of the present invention provides a semiconductor device including at least three independently accessible memory devices that can be independently tested. At least one of the memory devices has a memory capacity differing from the other memory devices. Selection signal lines independently provide each of the memory devices with a selection signal that activates the memory device.
Another aspect of the present invention provides a semiconductor device including at least three independently accessible memory devices that can be independently tested. At least one of the memory devices has a memory capacity differing from the other memory devices. A plurality of signal lines provide each of the memory devices with an address signal and a selection signal, for activating the memory devices. An inverter circuit is connected between a predetermined one of the memory devices and a predetermined one of the signal lines for providing the selection signal. The inverter circuit inverts the selection signal.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.